In the process of fabricating integrated circuits (ICs), electrical characteristics, such as resistance and capacitance values and transistor gain, of an actual fabricated circuit usually vary from ideal values in a circuit design. The differences in electrical characteristics can result in drawbacks, such as lower operating efficiency and improper circuit operation.
Trimmer process can be conducted to adjust the electrical characteristics of an IC to meet specifications. For trimmer process, there are two approaches: chip probing (CP) method which is conducted before packaging, and final test (FT) method which is conducted after packaging. To trim electrical characteristics of an IC, several fuses are designed and fabricated in the IC. In the CP method, the fuses in the IC are selectively blown off by a current produced by applying a voltage on a probe pad, or cut off by a laser. The FT method applies a voltage to a null pin to trim the fuses in the IC. Conventional methods zap the fuses by many extra external pads. For example, with reference to FIG. 1, several resistors 12 are serially connected between a node A and a node B, each of the resistors 12 is connected in parallel with a fuse 10 of which the two terminals are each connected to one of several pads 14, and the pads 14 are selectively applied with a voltage to blow off desired one or ones of the fuses 10 to be short circuit, so as to adjust the resistance value between the nodes A and B.
The IC package will introduce offset and thereby cause the FT method and CP method to have slightly different results. Thus the FT method is better than the CP method for the adjustment of circuit characteristics. However, the most limitation of the FT method is that the trimmer process needs one or more extra pins for control, which causes the pin count to increase and waste and is thus disadvantageous to shrink the size of an IC. Especially to the IC with high pin count, the FT method is not easy to apply. U.S. Pat. No. 6,703,885 to Fan et al. is to build up a circuit which can trim fuses by only two external pads. To zap fuses, however, this trimmer method may need very high current, maybe several hundred mA, and therefore, it will cost large chip area to implement a single device even MOS or bipolar junction transistor (BJT) in normal operation to provide such trimming current.